Faculty Information - Yamaji Takafumi

Yamaji Takafumi

Department / Course FACULTY OF COMPUTER AND INFORMATIONSCIENCES Department of Computer and Information Sciences

Job

Academic conference presentation
1.	2019/08/22	A Study on Noise and Occupied Area of Poly-phase Circuits (The 32nd Workshop on Circuits and Systems)
2.	2018/03/13	A proposal of an analog poly-phase integrator with complex coefficient
3.	2012/06	A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet^TM SoC in 65nm CMOS (Symposium on VLSI Circuits)
4.	2012/05	All-digital background calibration for time-interleaved ADC (IEEE International Symposium on Circuits and Systems (ISCAS))
5.	2011/02	A 570 fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop (IEEE International Solid-State Circuits Conference (ISSCC))
6.	2010/06	A 6-phase harmonic rejection down-converter with digital assist (Symposium on VLSI Circuits)
7.	2008/11	A low-jitter clock generator based on ring oscillator with 1/f noise reduction technique for next-generation mobile wireless terminals (IEEE Asian Solid-State Circuits Conference (ASSCC))
8.	2008/06	A direct conversion receiver adopting balanced three-phase analog system (Symposium on VLSI Circuits)
9.	2008/05	An area-efficient sampling rate converter using negative feedback technique (IEEE International Symposium on Circuits and Systems (ISCAS))
10.	2006/09	A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters (IEEE Custom Integrated Circuits Conference (CICC))
11.	2006/09	55-mW 1.2-V 12-bit 100-MSPS Pipeline ADCs for Wireless Receivers (European Solid-State Circuits Conference (ESSCIRC))
12.	2006/05	Balanced 3-phase analog signal processing for radio communications (IEEE International Symposium on Circuits and Systems (ISCAS))
13.	2005/09	A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS (IEEE Custom Integrated Circuits Conference (CICC))
14.	2005/09	55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers (European Solid-State Circuits Conference (ESSCIRC))
15.	2001/06	A temperature stable CMOS variable gain amplifier with 80-dB linearly controlled gain range (Symposium on VLSI Circuits)
16.	2001/02	A 2 GHz down-converter with a 3 dB bandwidth of 600 MHz using LO signal suppressing output buffer (IEEE International Solid-State Circuits Conference (ISSCC))
17.	2000/06	A Si 2-GHz 5-bit LO-phase-shifting downconverter for adaptive antennas (Symposium on VLSI Circuits)
18.	1998/02	An I/Q active balanced harmonic mixer with IM2 cancelers and a 45° phase shifter (IEEE International Solid-State Circuits Conference (ISSCC))
19.	1997/06	A Very Low Offset 1.9-GHz Si Mixer For Direct Conversion Receivers (Symposium on VLSI Circuits)
20.	1997/06	A 2 GHz balanced harmonic mixer for direct-conversion receivers (IEEE Custom Integrated Circuits Conference (CICC))
21.	2024/01/30	A study on the stability of feedback phase control for antenna beamforming